SanDisk SDDR-01 - ImageMate External Parallel CompactFlash Card Reader Manuel télécharger pdf (Page 53)

Preliminary CompactFlash Memory Card Product Manual

5.5.10 Device Control Register

(Address - 3F6[376]; Offset Eh)

This register is used to control the CompactFlash

Memory Card interrupt request and to issue an

ATA soft reset to the card. The bits are defined as

follows:

D7 D6 D5 D4 D3 D2 D1 D0

X X X X 1 SW Rst -IEn 0

Bit 7 This bit is an X (don't care).

Bit 6 This bit is an X (don't care).

Bit 5 This bit is an X (don't care).

Bit 4 This bit is an X (don't care).

Bit 3 This bit is ignored by the CompactFlash Memory Card.

Bit 2 (SW Rst) This bit is set to 1 in order to force the CompactFlash Memory Card to perform an AT Disk controller Soft

Reset operation. This does not change the PCMCIA Card Configuration Registers (4.3.2 to 4.3.5) as a

hardware Reset does. The Card remains in Reset until this bit is reset to '0'.

Bit 1 (-IEn) The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the

CompactFlash Memory Card are disabled. This bit also controls the Int bit in the Configuration and Status

Bit 0 This bit is ignored by the CompactFlash Memory Card.

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SanDisk SDDR-01 - ImageMate External Parallel CompactFlash Card Reader Manuel Page 53